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1 ltc1536 1536fa precision triple supply monitor for pci applications 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1536 pushbutton reset pci local bus r pu selected to meet rise time slew rate requirements (1k min) 5v 5% 3.3v 0.3v 0.1 f r pu rst 1536 ta01 pwr good 0.1 f motherboard pci rst generation time (20ns/div) voltage (1v/div) 5 4 3 2 1 0 1536 ta02 v cc5 = 5v to 3v step v cc3 = v cca = 3.3v 4.7k pull-up from rst to v cc3 rst v cc5 power fail waveform 5v dropping below 3.3v by 300mv simultaneously monitors 5v, 3.3v and adjustable inputs guaranteed threshold accuracy: 0.75% low supply current: 100 a internal reset time delay: 200ms manual pushbutton reset input active low and active high reset outputs active low ?oft?reset output power supply glitch immunity guaranteed reset for either v cc3 1v or v cc5 1v meets pci t fail timing specifications rev 2.1 8-pin so and msop packages the ltc 1536 is designed for pci local bus applications with multiple supply voltages that require low power, small size, high speed and high accuracy supply monitoring. for 3.3v and 5v supplies that are > 500mv below spec or for the condition when the 5v supply falls below the 3.3v supply, the ltc1536 has a very fast response time capable of meeting the pci t fail timing specification. tight 0.75% threshold accuracy and glitch immunity ensure reliable reset operation without false triggering. the rst output is guaranteed to be in the correct state for v cc5 or v cc3 down to 1v. the 100 a typical supply current makes the ltc1536 ideal for power-conscious systems. a manual pushbutton reset input provides the ability to generate a very narrow ?oft?reset pulse (100 s typ) or a 200ms reset pulse equivalent to a power-on reset. both srst and rst outputs are open-drain and can be or-tied with other reset sources. pci-based systems desktop computers notebook computers intelligent instruments portable battery-powered equipment network servers descriptio u features applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 ltc1536 1536fa a u g w a w u w a r b s o lu t exi t i s terminal voltage v cc3 , v cc5 , v cca .................................... 0.3v to 7v rst, srst ............................................ 0.3v to 7v rst ......................................... 0.3v to v cc3 + 0.3v pbr .......................................................... 7v to 7v operating temperature range ltc1536c .............................................. 0 c to 70 c ltc1536i ............................................ 40 c to 85 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c wu u package / o rder i for atio order part number order part number ltc1536cms8 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so v cc3 v cc5 v cca gnd pbr srst rst rst t jmax = 125 c, ja = 150 c/ w 1 2 3 4 v cc3 v cc5 v cca gnd 8 7 6 5 pbr srst rst rst top view ms8 package 8-lead plastic msop t jmax = 125 c, ja = 160 c/ w ms8 part marking ltbv s8 part marking 1536 1536i ltc1536cs8 ltc1536is8 (notes 1, 2) order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts specified with wider operating temperature ranges. electrical characteristics symbol parameter conditions min typ max units v rt3 reset threshold v cc3 0 c t a 70 c 2.962 2.985 3.000 v ?0 c t a 85 c 2.925 2.985 3.008 v v rt5 reset threshold v cc5 0 c t a 70 c 4.687 4.725 4.750 v ?0 c t a 85 c 4.625 4.725 4.762 v v rta reset threshold v cca 0 c t a 70 c 0.992 1.000 1.007 v ?0 c t a 85 c 0.980 1.000 1.007 v v cc v cc3 or v cc5 operating voltage rst in correct logic state 17v i vcc3 v cc3 supply current pbr = v cc3 100 200 a i vcc5 v cc5 input current v cc5 = 5v 10 20 a i vcca v cca input current v cca = 1v ?5 0 15 na t rst reset pulse width rst low with 10k ? pull-up to v cc3 0 c to 70 c 140 200 280 ms 40 c to 85 c 140 200 300 ms t srst soft reset pulse width srst low with 10k ? pull-up to v cc3 50 100 200 s t uv v cc undervoltage detect to rst v cc5 , v cc3 or v cca less than reset 13 s threshold v rt by 1% the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc3 = 3.3v, v cc5 = 5v, v cca = v cc3 unless otherwise noted.
3 ltc1536 1536fa symbol parameter conditions min typ max units i pbr pbr pull-up current pbr = 0v, 0 c t a 70 c 3710 a pbr = 0v, 40 c t a 85 c 3715 a v il pbr, rst input low voltage 0.8 v v ih pbr, rst input high voltage 2v t pw pbr min pulse width 40 ns t db pbr debounce deassertion of pbr input to srst 20 35 ms output (pbr pulse width = 1 s) t pb pbr assertion time for transition pbr held less than v il , 0 c to 70 c 1.4 2.0 2.8 s from soft to hard reset mode pbr held less than v il , 40 c to 85 c 1.4 2.0 3.0 s v ol rst output voltage low i sink = 5ma 0.15 0.4 v i sink = 100 av cc3 = 1v, v cc5 = 0v 0.05 0.4 v 0 c t a 70 cv cc3 = 0v, v cc5 = 1v 0.05 0.4 v v cc3 = 1v, v cc5 = 1v 0.05 0.4 v i sink = 100 av cc3 = 1.1v, v cc5 = 0v 0.05 0.4 v ?0 c t a 85 cv cc3 = 0v, v cc5 = 1.1v 0.05 0.4 v v cc3 = 1.1v, v cc5 = 1.1v 0.05 0.4 v srst output voltage low i sink = 2.5ma 0.15 0.4 v rst output voltage low i sink = 2.5ma 0.15 0.4 v v oh rst output voltage high (note 3) i source = 1 a v cc3 ?1 v srst output voltage high (note 3) i source = 1 a v cc3 ?1 v rst output voltage high i source = 600 a v cc3 ?1 v t phl propagation delay rst to rst c rst = 20pf 25 ns high input to low output t plh propagation delay rst to rst c rst = 20pf 45 ns low input to high output t fail v cc5 or v cc3 0.5v undervoltage v cc5 drops below 4.25v or v cc3 drops 150 450 ns to rst (note 4) below 2.5v (note 5) t pf v cc5 < (v cc3 ?300mv) rst (note 4) v cc5 drops below v cc3 by 300mv 50 90 ns (note 6) note 4: conforms to pci local bus specification rev 2.1, sect. 4.3.2 for t fail . note 5: v cc3 or v cc5 falling at 0.1v/ s, time measured from v rtx ?500mv to rst at 1.5v. note 6: v cc5 falling from 5v to 3v in 10ns, time measured from v cc5 = (v cc3 ?300mv) to rst at 1.5v. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: the output pins srst and rst have weak internal pull-ups to v cc3 of 6 a. however, external pull-up resistors may be used when faster rise times are required. electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc3 = 3.3v, v cc5 = 5v, v cca = v cc3 unless otherwise noted.
4 ltc1536 1536fa typical perfor m a n ce characteristics uw v cca input current vs input voltage temperature ( c) ?5 0 i vcc3 ( a) 20 40 60 80 140 120 ? 35 55 1536 g01 100 ?5 15 75 i vcc3 vs temperature input voltage (v) 0.8 ? input current (na) ? ? 0 1 0.9 1.0 1.1 1.2 1536 g03 2 3 0.85 0.95 1.05 1.15 t a = 25 c temperature ( c) ?5 0 i vcc5 ( a) 2.5 5.0 7.5 10.0 20.0 15.0 ? 35 55 1536 g02 17.5 12.5 ?5 15 75 i vcc5 vs temperature temperature ( c) ?0 v cc5 threshold voltage, v rt5 (v) 4.750 4.745 4.740 4.735 4.730 4.725 4.720 4.715 4.710 4.705 4.700 ?0 20 40 1536 g04 ?0 0 60 80 100 v cc5 threshold voltage vs temperature v cca threshold voltage vs temperature temperature ( c) ?0 v cca threshold voltage, v rta (v) 1.005 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 ?0 20 40 1536 g06 ?0 0 60 80 100 v cc3 threshold voltage vs temperature temperature ( c) ?0 v cc3 threshold voltage, v rt3 (v) 60 1536 g05 ?0 20 ?0 80 0 40 100 3.010 3.005 3.000 2.995 2.990 2.985 2.980 2.975 2.970 2.965 2.960 pbr assertion time to reset vs temperature reset pulse width vs temperature temperature ( c) ?0 210 215 220 25 75 1536 g07 205 200 ?5 0 50 100 195 190 reset pulse width, t rst (ms) 225 ?oft?reset pulse width vs temperature temperature ( c) ?0 105.0 107.5 110.0 25 75 1536 g08 102.5 100.0 ?5 0 50 100 97.5 95.0 soft reset pulse width, t srst ( s) 112.5 temperature ( c) ?0 2.10 2.15 2.20 25 75 1536 g09 2.05 2.00 ?5 0 50 100 1.95 1.90 pbr assertion time to reset, t pb (sec) 2.25
5 ltc1536 1536fa typical perfor m a n ce characteristics uw v cc3 typical transient duration vs reset comparator overdrive v cca typical transient duration vs reset comparator overdrive v cc3 reset comparator overdrive, v rt3 ?v cc3 (v) 0.001 20 typical transient duration ( s) 30 40 45 50 0.01 0.1 1 1536 g10 10 0 25 35 15 5 reset occurs above curve v cca reset comparator overdrive, v rta ?v cca (v) 0.001 20 typical transient duration ( s) 30 40 0.01 0.1 1 1536 g12 10 0 25 35 15 5 reset occurs above curve v cc5 typical transient duration vs reset comparator overdrive v cc5 reset comparator overdrive, v rt5 ?v cc5 (v) 0.001 20 typical transient duration ( s) 30 40 45 0.01 0.1 1 1536 g11 10 0 25 35 15 5 reset occurs above curve rst output voltage vs supply voltage supply voltage, v cc (v) 0 rst output voltage (v) 3.0 4.0 5.0 4.0 1536 g13 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 1.0 2.0 3.0 0.5 4.5 1.5 2.5 3.5 5.0 v cc5 = v cc3 = v cca 4.7k pull-up from rst to v cc5 t a = 25 c undervoltage response time vs temperature time (1 s/div) voltage (500mv/div) 1536 g15 v cc3 85 ?0 rst margin device threshold pci spec 25 t fail spec v cc3 falling from 3.3v to 2.3v at ( 0.1v/ s) rst output voltage vs supply voltage supply voltage, v cc (v) 0 rst output voltage (v) 3.0 4.0 5.0 4.0 1536 g16 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 1.0 2.0 3.0 0.5 4.5 1.5 2.5 3.5 5.0 v cc5 = v cc3 = v cca rst pin loaded with 10m ? to gnd t a = 25 c power-fail response time vs temperature time (20ns/div) voltage (1v/div) 1536 g14 v cc5 rst 85 ?0 25
6 ltc1536 1536fa pi n fu n ctio n s uuu v cc3 (pin 1): 3.3v sense input and power supply pin for the ic. bypass to ground with 0.1 f ceramic capacitor. v cc5 (pin 2): 5v sense input. used as gate drive for rst output fet when the voltage on v cc5 is greater than the voltage on v cc3 . v cca (pin 3): 1v sense, high impedance input. can be used as a logic input with a 1v threshold. if unused it can be tied to either v cc3 or v cc5 . gnd (pin 4): ground. rst (pin 5): reset logic output. active high cmos logic output, drives high to v cc3 , buffered compliment of rst. an external pull-down on the rst pin will drive this pin high. rst (pin 6): reset logic output. active low, open-drain logic output with weak pull-up to v cc3 . can be pulled up greater than v cc3 when interfacing to 5v logic. v cc3 soft reset reset 3 v cca 2 v cc5 to power detect 8 pbr 7 srst 4 gnd ref pbr timer 200ms reset generator power detect/ gate drive v cc3 6 rst 5 v cc3 v cc3 v cc5 rst 6 a v cc3 7 a 6 a + fast + fast + slow + fast + slow + slow 1 v cc3 to power detect and v cc internal 1326 bd block diagra m w asserted when one or more of the supplies are below trip thresholds and held for 200ms after all supplies become valid. also asserted after pbr is held low for more than two seconds and for an additional 200ms after pbr is released. srst (pin 7): ?oft?reset. active low, open-drain logic output with weak pull-up to v cc3 . can be pulled up greater than v cc3 when interfacing to 5v logic. asserted for 100 s after pbr is held low for less than two seconds and released. pbr (pin 8): pushbutton reset. active low logic input with weak pull-up to v cc3 . can be pulled up greater than v cc3 when interfacing to 5v logic. when asserted for less than two seconds, outputs a soft reset 100 s pulse on the srst pin. when pbr is asserted for greater than two seconds, the rst output is forced low and remains low until 200ms after pbr is released.
7 ltc1536 1536fa ti i g diagra s w w u v cc monitor timing pushbutton reset function timing t < t pb t pb t rst t db t srst 1536 td02 pbr rst srst t rst 1536 td01 v rtx v ccx rst t fail fast undervoltage detect t fail 500mv 1536 td03 v cc3 or v cc5 v rtx slew rate 0.1v/ s rst t pf 300mv 1536 td04 v cc5 fall time 10ns, v cc3 = 3.3v rst 3.3v power-fail detect applicatio n s i n for m atio n wu u u operation the ltc1536 is a low power, high accuracy triple supply monitoring circuit. this reset generator has two basic functions: generation of a reset when power supplies are out of range, and generation of a reset or ?oft?reset when the reset button is pushed. the ltc1536 has the added feature that when the reset supplies are grossly undervolt- age there is a very short delay from undervoltage detect to assertion of rst. supply monitoring all three v cc inputs must be above predetermined thresh- olds for 200ms before the reset output is released. the ltc1536 will assert reset during power-up, power-down and brownout conditions on any one or more of the v cc inputs. on power-up, either the v cc5 or v cc3 pin can power the drive circuits for the rst pin. this ensures that rst will be low when either v cc5 or v cc3 reaches 1v. as long as any one of the v cc inputs is below its predetermined threshold, rst will stay a logic low. once all of the v cc inputs rise above their thresholds, an internal timer is started and rst is released after 200ms. rst outputs the inverted state of what is seen on rst. rst is reasserted whenever any one of the v cc inputs drops below its predetermined threshold and remains asserted until 200ms after all of the v cc inputs are above their thresholds. on power-down, once any of the v cc inputs drops below its threshold, rst is held at a logic low. a logic low of 0.4v is guaranteed until v cc3 and v cc5 drops below 1v. pushbutton reset the ltc1536 provides a pushbutton reset input pin. the pbr input has an internal pull-up current source to v cc3 . if the pbr pin is not used it can be left floating.
8 ltc1536 1536fa when the pbr is pulled low for less than t pb ( 2 sec), a narrow (100 s typ) soft reset pulse is generated on the srst output pin after the button is released. the push- button circuitry contains an internal debounce counter which delays the output of the soft reset pulse by typically 20ms. this pin can be or-tied to the rst pin and issue what is called a ?oft?reset. the srst thereby resets the microprocessor without interrupting the dram refresh cycle. in this manner dram information remains undis- turbed. alternatively, srst may be monitored by the processor to initiate a software-controlled reset. when the pbr pin is held low for longer than t pb ( 2 sec), a standard reset is generated. once the 2-second period has elapsed, a reset signal is produced by the pushbutton logic, thereby clearing the reset counter. once the pbr pin is released, the reset counter begins counting the reset period (200ms nominal). consequently, the reset outputs remain asserted for approximately 200ms after the button is released. fast undervoltage for pci applications the ltc1536 is designed for pci local bus applications that require reset to be asserted quickly in response to one or both of the power supply rails (5v and 3.3v) going out of spec. the spec for t fail and t pf are met with enough margin to give the designer the ability to add follow-on logic as needed by system requirements. the v cca pin can be used to monitor the ?ower good?signal and keep reset applied until both supplies are in spec and the power good signal is high. glitch immunity and fast undervoltage detection the ltc1536 achieves its high speed characteristics while maintaining glitch immunity by using two sets of com- parators. the v cc5 and v cc3 sense inputs each have two comparators set at different thresholds. a slow, very accurate comparator monitors the supply for precision undervoltage detection. in parallel, but with a threshold 250mv lower than the precision threshold, is a very fast comparator that detects when the supply is quickly going out of specification. because the fast comparator thresh- old is set 250mv above the pci specification, typical values for t fail can be negative. 3v or 5v power detect/gate drive the ltc1536 for the most part is powered internally from the v cc3 pin. the exception is at the gate drive of the output fet on the rst pin. on the gate to this fet is power detect circuitry used to detect and drive the gate from either the 3.3v pin or the 5v pin, whichever pin has the highest potential. this ensures the part pulls the rst pin low as soon as either input pin is 1v. extended esd tolerance of the pbr input pin the pbr pin is susceptible to esd since it can be brought out to a front panel in normal applications. the esd tolerance of this pin can be increased by adding a resistor in series with the pbr pin. a 10k resistor can increase the esd tolerance of the pbr pin to approximately 10kv. the pbr? internal pull-up current of 7 a typical means there is only 70mv (150mv max) dropped across the resistor. applicatio n s i n for m atio n wu u u typical applicatio n s n u 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1536 pci local bus 0.1 f 3.3v supply reset 5v supply 1536 ta08 0.1 f onboard device pci expansion board rst generation dual supply monitor (3.3v and 5v, v cca input monitoring ?ower good? 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1536 3.3v system reset 5v pwr good 1536 ta04
9 ltc1536 1536fa typical applicatio n s n u triple supply monitor (3.3v, 5v and adjustable) 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1536 3.3v system reset 100k 5v 1536 ta09 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1536 3.3v system reset *optional resistor extends esd tolerance of pbr input 8kv to 10kv 5v r2 r1 1536 ta03 adjustable supply or dc/dc feedback divider 10k* pushbutton reset srst tied to rst and or-tying other sources to rst to generate reset and reset 4.7k srst 6 a 6 a 3.3v ltc1536 pushbutton reset reset 1536 ta05 other open drain reset sources or-tied to reset 7 8 pbr rst rst v cc3 6 5 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1536 3.3v system reset 5v 22.1k 1% 1536 ta07 35.7k 1% ltc1435 adjustable reset trip threshold 2.74v 2.9v 2.8k 1% 6 v osense using v cca tied to dc/dc feedback divider reset valid for v cc3 down to 0v in a dual supply application
10 ltc1536 1536fa package descriptio n u ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 0204 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc
11 ltc1536 1536fa package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
12 ltc1536 1536fa ? linear technology corporation 1997 lt 0106 rev a ?printed in the usa typical applicatio n s n u part number description comments ltc690 5v supply monitor, watchdog timer and battery backup 4.65v threshold ltc694-3.3 3.3v supply monitor, watchdog timer and battery backup 2.9v threshold ltc699 5v supply monitor and watchdog timer 4.65v threshold ltc1232 5v supply monitor, watchdog timer and pushbutton reset 4.37v/4.62v threshold ltc1326 micropower precision triple supply monitor 4.725v, 3.118v, 1v thresholds ( 0.75%) ltc1326-2.5 micropower precision triple supply monitor 2.363v, 3.118v, 1v thresholds ( 0.75%) related parts quad supply monitor: 12v: undervoltage, overvoltage 5v: undervoltage, overvoltage 3.3v: undervoltage, overvoltage 12v: undervoltage + + + + a pwr good b 2 12v 3 ltc1444 4 5 1 6 7 1.21m 1.21m 1% 2.37m 1% 3.3v 0.3v 5v 5% 12v 5% 12v 10% 1.05m 1% 102k 1% 100k 0.1 f optional 1m 4.02m 1% c 16 d 15 9 hyst 1536 ta07 11 10 12 13 8 14 9.31m 1% 1.21m 1% ref 1.221v 10.7m 1% 5v system reset 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1536 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com

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